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| author | Your Name <[email protected]> | 2026-08-18 15:31:18 -0700 |
|---|---|---|
| committer | Your Name <[email protected]> | 2026-08-18 15:31:18 -0700 |
| commit | 19f9e5e972ddd4e08fa99f96a0ccc4101b86c9b1 (patch) | |
| tree | 47ca6c2cddcd06167158769d212b845db154fc27 /models/Pershin_DiVentra_memristor.cir | |
| parent | 11828573d0725da5564ba8676a31d62605152e5b (diff) | |
included models
Diffstat (limited to 'models/Pershin_DiVentra_memristor.cir')
| -rw-r--r-- | models/Pershin_DiVentra_memristor.cir | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/models/Pershin_DiVentra_memristor.cir b/models/Pershin_DiVentra_memristor.cir new file mode 100644 index 0000000..b6d2f16 --- /dev/null +++ b/models/Pershin_DiVentra_memristor.cir @@ -0,0 +1,7 @@ +.subckt memristor pl mn PARAMS: Ron=1K Roff=10K Rinit=5K alpha=0 beta=1E13 Vt=4.6 +Bx 0 x I='(f1(V(pl,mn))>0) && (V(x)<Roff) ? {f1(V(pl,mn))}: (f1(V(pl,mn))<0) && (V(x)>Ron) ? {f1(V(pl,mn))}: {0}' +Cx x 0 1 IC={Rinit} +R0 pl mn 1E12 +Rmem pl mn r={V(x)} +.func f1(y)={beta*y+0.5*(alpha-beta)*(abs(y+Vt)-abs(y-Vt))} +.ends |